Among test methods of a semiconductor integrated circuit, there is a test method that is called a built-in self-test (BIST) method. According to the BIST method, in a semiconductor integrated circuit that includes a pseudo random number pattern generator and a code compressor, a pseudo random number pattern is applied to a test target logic, and a compression result of a response pattern and an expected value are compared with each other, thereby enabling self-diagnosis.
The BIST is configured to include a pseudo random number test pattern generator that applies a large amount of patterns to a test circuit that has been scan-designed and a code compressor that determines the good or not by compressing output response series and performing a comparison operation in only final codes. In general, in a pattern generator and a patter compressor, a linear feedback shift register is used. In the pattern generator that uses the linear feedback shift register, except for “0”, all patterns can be pseudo-randomly generated.
As examples of a document that has described the BIST including the pattern generator, there are JP-A-Hei10(1998)-170609 and JP-A-2001-174515.
According to a technology that is described in JP-A-Hei10(1998)-170609, a test circuit and a test target LSI are formed. In this case, the test circuit has a plurality of shift registers that are configured to connect a test target circuit and a plurality of flip-flops. In the test target LSI, a random number pattern generator and a code compressor, each of which is composed of a linear feedback shift register, are incorporated. In this case, a clock frequency divider is incorporated, and a shift clock that is applied to the random number pattern generator is also applied to the clock frequency divider. The clock frequency divider changes a period of the shift clock to a period of ½, ¼,or ⅛ in accordance with signals input from a clock control pin, and applies the shift clock to the code compressor and the plurality of shift registers.
According to a technology that is described in JP-A-2001-174515, a flip-flop group in a logic integrated circuit is connected by scan chains, a random number generation circuit and a code compressor are incorporated in the logic integrated circuit, a clock signal is supplied to the flip-flop group, the random number generation circuit, and the code compressor, random number patterns that are sequentially generated in the random number generation circuit in synchronization with the clock signal are written in the flip-flop group and shift-scanned, and the result thereof is compressed by the code compressor. In addition, a portion or all of clock signals of latch elements that constitute the random number generation circuit are temporarily blocked to temporarily stop generation and output of random numbers, and an average value of a continuous length of 1 or 0 of random numbers that shift-scan the flip-flop group in the logic integrated circuit is increased.